Method of high selectivity sac etching

ABSTRACT

A method for SAC etching is provided involving a) etching a Si wafer having a nitride present thereon with a first etching gas containing a first perfluorocarbon and carbon monoxide, and b) etching the resultant Si wafer having an initially etched nitride photoresist thereon with a second etching gas containing a second perfluorocarbon in the substantial absence of carbon monoxide, wherein the etching steps a) and b) are performed at high RF power and low pressure compared to conventional processes to provide higher selectivity etching and a larger process window for SAC etching, as well as the ability to perform SAC etching and island contact etching under the same conditions with high verticality of the island contact and SAC walls.

TECHNICAL FILED

[0001] The present invention provides a method for providing high selectivity in self-aligned contact (SAC) etching by use of a high ion energy plasma generated with high RF power at low process pressure.

BACKGROUND ART

[0002] Self-aligned Contact (SAC) is one of the key technologies in ULSI (Ultra Large Scale Integration) fabrication. SAC can relax the alignment margin in photolithography. The selectivity to SiN at the corner (shoulder) is the most important issue in SAC etching.

[0003] Therefore, over the years of process development in SAC etching, heavy polymerization chemistries have been relied on in order to get high selectivity to nitride (i.e. ratio of [oxide etch rate]/[nitride etch rate]), because the nitride corner is exposed to plasma for a longer time or a longer over-etching than the bottom nitride. For achieving high corner selectivity, gases having high C/F atomic ratio, such as C₄F₈, are used in SAC etching. Additionally, CH₃F or CH₂F₂ addition is reported to increase corner selectivity. Unfortunately, high selectivity SAC etching with these gases is also accompanied by the etch stop phenomenon, where the etching is incomplete, stopping in the middle of the hole due to fast polymerization, particularly in narrow slits between the gate electrodes. The width of the slit will be narrower with the shrinkage of the minimum feature sizes in LSIs. Thus it is becoming ever more difficult to keep the corner selectivity without encountering etch stop in the slit.

[0004] On the other hand, while the nitride corner is exposed, oxide in a narrow slit between the gate electrode is continuously being etched and oxygen is released which slows down the polymer formation on the nitride corner. It is also known that there is usually observed a lower selective portion on the small overlapped nitride corner and at the worst case, this phenomenon causes an electrical short problem.

[0005] The etch stop phenomenon is particularly a problem when the etching parameters must be controlled in a narrow process window. This requires very close control of etching parameters. On the other hand, the superior and strong carbon rich polymerization often cases various other problems such as an etching profile micro loading between dense and isolated patterns, a slow etching rate, low throughput and short mean time between wet cleanings (MTBWC).

[0006] Conventionally, it has been essential to separate island contact etching on a peripheral area or gate contact etching processes from SAC etching because it is very difficult to get a vertical profile and maintain enough good contact resistance when etched at the same time or with the same process due to superior and strong carbon rich polymerization.

[0007] One conventional method for SAC etching employs dipole ring magnetron reactive ion etching (DRMRIE). In DRMRIE, the plasma ion density is considered medium density and is from 10¹⁰-10¹¹ ions/cm³. This provides a very stable, repeatable plasma with high selectivity. Unfortunately, the conventional use suffers from a low etching rate and tends to leave the corners from the etching process too sharp. Conventional etching uses a plasma generated using a pressure of from 50-60 mT and an RF power of 1300-1500W.

[0008] Additionally, in conventional etching processes, the way to achieve higher selectivity is considered to be by increasing the bottom temperature (temperature at the bottom of the layer being etched) and to reduce the power. Unfortunately, these two procedures tend to cause etch stopping, described above.

[0009] Table 1 below provides a summary of various issues present in the SAC etching process conventionally practiced. TABLE 1 Table of various process issues/requirements of SAC etching Requirements on process integration Requirements on Process Issues around SAC etch SAC etching process (1) Current leakage To minimize the To control the etch CD- between W-plug and misalignment of the bias on top of the contact Inter-connect line Inter-connect line hole (2) Incomplete etching to optimize the cell To have enough big down to the Si layout to have enough etching capability substrate contact space (3) Electrical short To optimize the thick- To generate C-rich between W-plug and ness and materials of polymer to obtain high Poly Gate the Gate Cap/Spacer, selectivity to the Nitride To control the overlap or SiON amount as much as possible by the Lithography process (4) Small Bottom CD N/A To optimize the etching on the island contact chemistries hole if it exists (5) Etching profile U- N/A To optimize the etching loading between dense chemistries and isolated areas

[0010] Accordingly, a process is needed for SAC etching that avoids the etch stop phenomenon, while maintaining high selectivity and high etching rate, with a large process window.

DISCLOSURE OF INVENTION

[0011] Accordingly, one object of the present invention is to provide a method for SAC etching that provides high SiO/SiN selectivity while avoiding etch stop.

[0012] A further object of the present invention is to provide a method for SAC etching that provides high etch rate and high selectivity within a large process window.

[0013] A further object of the present invention is to provide a method for SAC etching that can be performed while simultaneously providing island contact etching with high verticality of the island contact walls.

[0014] These and further objects of the present invention have been satisfied by the discovery of a method for SAC etching comprising:

[0015] a) etching a wafer having a silicon oxide layer above a silicon nitride layer present thereon with a first etching gas comprising a first perfluorocarbon and carbon monoxide and,

[0016] b) etching the resultant wafer having an initially etched silicon nitride thereon with a second etching gas comprising a second perfluorocarbon in the absence of carbon monoxide.

BRIEF DESCRIPTION OF DRAWINGS

[0017] A more complete appreciation of the invention and many of the attendant advantages thereof will be readily obtained as the same becomes better understood by reference to the following detailed description when considered in connection with the accompanying drawings, wherein;

[0018]FIG. 1 shows a schematic of a DRMRIE system suitable for use in practicing the present process.

[0019]FIG. 2 shows a schematic representation of one embodiment of a wafer to be etched by the present process.

[0020]FIG. 3A shows a schematic representation of SAC and island contacts after the descum etch and first etching stage of the present process.

[0021]FIG. 3B shows a schematic representation of SAC and island contacts after the second etching stage of the present process.

[0022]FIG. 3C shows a schematic representation of SAC and island contacts after the final nitride removal step of one embodiment of the present process.

[0023]FIGS. 4A and 4B are views for showing electron micrographs of actual etched products clearly illustrating the smooth roundness of the corners and high verticality of the etched walls.

[0024]FIG. 5 shows a magnified view of a transistor gate.

BEST MODE FOR CARRYING OUT OF THE INVENTION

[0025] The present invention relates to a method for etching, preferably for preparation of both SAC and vertical island contact, which provides high SiN selectivity with smooth and rounded shape in SAC etching and nearly vertical walls in island contacts. The present process uses a two stage etching process using a high energy plasma generated with high RF power under low pressure.

[0026] The two steps of the present process can be generally described as (1) an initial stage using a combination of a perfluorocarbon and carbon monoxide gases, followed by (2) a second stage using a perfluorocarbon gas in the absence of carbon monoxide. The two stages can be performed at the same RF power and pressure or at different RF powers, different pressures, or both.

[0027] As the perfluorocarbon (PFC) gas, any conventional perfluorocarbon used for etching can be used. Preferably, the PFC is any of the PFC's having empirical formulae C₃F₆, C₄F₆, C₄F₈ or C₅F₈, more preferably of the formulae and structures:

[0028] most preferably c-C₄F₈.

[0029] The first stage of the process of the present invention combines PFC gas and carbon monoxide (CO) gas. Preferably the first stage combines these two gases with an inert gas carrier such as argon, and either oxygen (O₂) or nitrogen (N₂).

[0030] The second stage of the present process uses a similar reaction gas mixture as the first stage, without the presence of carbon monoxide.

[0031] The first and second stages can use the same PFC gas or different PFC gases. The first and second stages can be performed in discrete and separate steps with the DRMRIE apparatus being turned off between steps to allow change of the reaction gas atmosphere, or can be connected by a transitional period wherein the DRMRIE apparatus continues operating while the atmosphere is changed and equilibrated, resulting in a transitional stage between the first and second stages of the process.

[0032] When performing the present process, any size target can be used, with 8 inch wafers being preferred. In the preferred 8 inch wafer embodiment, the preferred RF power for plasma generation is 1700 watts or more, at a pressure of 30 mTorr or less. Under the conditions of the present invention, the etching rate of TEOS or BPTEOS in the first stage (PFC and CO) is on the order of 6000 Å/min, compared to conventional etch rates of 3800-4000 Å/min.

[0033] When using the present invention process for forming island contacts, the present process provides walls that are nearly vertical. For TEOS (oxide layer deposited by plasma-CVD from tetraethoxysilane), the present process provides wall angles of from 87.5-88°, compared to 84-85° for conventional etching (where 90° would be perfectly vertical walls). Regardless of the layer material used, the present process provides significant improvements in wall angle. For example, etching of BPTEOS (TEOS doped with 6 wt % Boron and 4 wt % Phosphate and annealed at 850-950° C.) using the present process gives wall angles of ˜88.50, compared to 87.5° for conventional processes. (In the etching art, as one approaches 90°, each 10 of improvement becomes quite a significant difference.) Similar results are obtained also with AMAT Gigafill, a similar product commercially available from Applied Material and Technology of California.

[0034] In the etching gas of the present invention, the inert carrier gas can be any inert gas suitable for plasma etching, preferably Ar, He or Xe, most preferably Ar. The gas mixture can contain either of O₂ or N₂. When N₂ is used, the feed rate of N₂ is preferably 10 times higher than the feed rate Of O₂ normally used.

[0035] The preferred gas feed rates (in standard cubic centimeter, SCCM) for each stage are: Stage PFC CO Inert Gas O₂ (N₂) 1 20-27 50-100 150-300 7-12 (70-120) 2 10-20 0 450-550 5-10 (50-100)

[0036] Most preferably the gas feed rates are: Stage PFC CO Inert Gas O₂ 1 25 50 250 10 2 20 0 500 10

[0037] The PFC/O₂ flow ratio is more important in the process than the absolute flow rate. The preferred PFC/O₂ flow ratio is from 2:1 to 3:1, particularly where the PFC is C₄F₈.

[0038] Also important in the process of the present invention is the temperature at the bottom of the wafer. The preferred bottom temperature is from 50-60° C.

[0039] The present invention process preferably is performed using a dipole ring magnetron reactive ion etching (DRMRIE) system, depicted in FIG. 1. In one embodiment, there are 32 pieces of dipole magnets 10 each having from 60 to 280 Gauss of magnetic force. These 32 dipole magnets rotate around an aluminum body process chamber 20 at approximately 20 rpm, producing a 120 Gauss averaged magnetic field. This magnetic field enhances the plasma density due to ExB drift. The process chamber (20) is evacuated with a turbo molecular pump (not shown) to produce the desired process pressure. The lower electrode 30 having RF power of 13.56 MHz is equipped with an electrically static chuck for wafer chucking, with backside He gas cooling to control the backside temperature of the wafer 50, to 50-60° C. Reaction process gases are introduced to the etching chamber through the upper electrode (40) gas distribution.

[0040]FIG. 2 shows a schematic representation of one embodiment of a wafer 50 to be etched by the present process. The test wafer 50 is preferably stacked with 800 nm photoresist (51)/10 nm to 100 nm TEOS (52)/250 nm BPTEOS (53)/poly gate(consisting of the polysilicon (59) and the tungsten silicide (58) as shown in FIG. 5)/Si substrate (54) with 0.20 μm to 0.27 μm hole size. The gate portion comprises a nitride cap (55), with nitride spacers (56) on either side of nitride cap (55), with the assembly surrounded by a nitride liner (57).

[0041] The nitride cap can be any nitride material, preferably nitride or nitride/SiON. The thickness of the nitride cap is preferably 200-250 nm, with 230 nm preferred for SiON. The nitride spacers are preferably 60 nm thick and the nitride liner is preferably 30 nm thick.

[0042] In FIG. 3A, a SAC and an island contact are shown after an initial descum etch and the first etching stage of the present invention process (also called a “break through” etch). In the Figure, the BPTEOS material (53) has been removed down to the corner of the nitride cap (55) and nitride spacer (56), breaking through the nitride liner (57). This etch step is performed to provide etching to a level of 100-1000 Å below the nitride cap corner.

[0043] In FIG. 3B, the process has progressed to after the second etching stage, with approximately 220 Å of target loss at the corner of the nitride cap (55), and with good roundness of corners beginning to show. Nitride liner (57) is still present at the bottom of the etching well in both SAC and island contacts.

[0044] In FIG. 3C, the final nitride removal step has been performed to remove the remaining excess nitride liner (57) from the etching site, with the nitride removal also etching partially into the base support (Si wafer (54)), up to a level of about 200 Å.

[0045]FIGS. 4A and 4B show electron micrographs of actual etched products clearly illustrating the smooth roundness of the corners and high verticality of the etched walls.

[0046] The preferred embodiments of the present process start with an initial scum etch step using PCF and O₂ (or N₂) for 10 seconds or less. This is followed by the two stage etching described above, with a final nitride etch. The first stage etch of the present invention is performed for a time period sufficient to etch to a level of 100-1000 Å below the nitride cap corner (See FIG. 3A). It is preferred to conduct the etching process in both stages, such that a distance of at least 300 Å is maintained between the tungsten silicide corner and the etching front. The distance between the tungsten silicide corner and etching point is more preferably at least 600 Å, most preferably 800-900 Å. In the final product, following both etching stages and final bottom nitride removal, the corner nitride on the poly gate should have 250-350 Å of nitride removed from the above stated thicknesses.

[0047] The second stage etch is performed to provide the corners of the nitride with a rounded nature to maintain sufficient distance for the poly gate electrodes. The final nitride etch is performed to complete the process and clean the remaining nitride protective layer off.

[0048] The two stage process of the present invention can be used for any type of SAC etching, including but not limited to shallow SAC to deep SAC. Additionally, as noted above, the present process can be used for island contact etching to obtain more nearly vertical walls. One unique aspect of the present process is that it is possible to conduct both SAC etching and island contact etching at the same time using the same conditions, while obtaining outstanding results both in process window for the SAC etching and in wall verticality for the island contact etching.

[0049] Use of a single stage PFC process using only a CO combination plasma with high ion energy generated with high RF power and low process pressure, provides a vertical etching profile and solves micro loading between dense and isolated areas, but the etching profile around the corners is too sharp. Depending on the alignment (or misalignment) of the mask, this results in the distance between the poly gate electrodes being not enough to insulate. In order to get a rounded shape on the corners and sufficient distance between the corners of the poly gate electrodes, the present invention uses no CO plasma in the second stage.

[0050] Using the present invention two stage process, the conventionally seen carbon rich polymer deposits on the SiN corners, as well as any etching profile micro loading on the end pattern in very isolated areas, do not appear, even with no CO plasma in the second step.

EXAMPLE Example 1

[0051] As a typical example of this invention, one of the etching recipes is described in the following for a high etch rate SAC etching process, with vertical island Contact etching at the same time.

[0052] Etching Recipe (1):

[0053] Descum Etch:

[0054] 40 mT 1400W

[0055] CF₄/Ar/O₂=80/160/20 sccm, 7 sec

[0056] ILD Etch-1:

[0057] 30 mT 1700W

[0058] C₄F₈/CO/Ar/O₂=25/50/250/10 sccm, 60/60° C. (note in this and the following examples, this represents temp of top electrode and wall/temp of cathode)

[0059] Back He C/E=7/30T, 45 sec

[0060] ILD Etch-2:

[0061] 60 mT 1700W C₄F₈/CO/Ar/O₂=20/00/500/10 sccm, 60/60° C.

[0062] Back He C/E=7/30T, 75 sec

[0063] Nitride Etch:

[0064] 50 mT 800W CHF₃/Ar/O₂=10/100/20sccm,

[0065] Process Gap =37 mm,

[0066] Back He C/E=7/40T, 9 sec

[0067] The etch rate of ILD-Etch.1 (1^(st) stage etching) was approximately 1.5 times faster than conventional SAC etching.

[0068] Moreover, combined with ILD-Etch.2 (2^(nd) stage etching), the corner etching profile had a smooth and rounded shape. The shortest distance with etching recipe (1) between the corners of the poly gate electrode was approximately 1.5 times longer than that conventional SAC etching recipes after the bottom nitride removal.

[0069] In addition to the ILD-1 etching conditions described in etching recipe (1), the etching capability with 10 KA TEOS was investigated.

[0070] Increasing the gas flow of C₄F₈ and O₂ while maintaining the same gas ratio, gave up to 1.3 times faster etch rate and could provide a higher etch rate SAC etching simultaneously with vertical island Contact etching with greater than 88° walls at the 0.27 μm hole size, without any etch stop, micro loading or other issues.

[0071] In addition, compared with conventional SAC etching, a two step etching approach with C₄F₈ chemistries described in etching recipe (1) would expect to extend MTBWC approximately twice and more. Therefore this result not only increases SAC etching process windows but also decreases wafer processing steps, simplifies wafer processing and contributes to cost reduction and yield increase in ULSI fabrication.

[0072] The following Tables 2-4 provide process operation ranges for ILD-1, ILD-2 and overall process temperature operation ranges. TABLE 2 Process Operation Range of 1^(st) Stage of Recipe (1) Press RF Power C₄F₈ CO Ar O₂ Gap (mT) (Watts (sccm) (sccm) (sccm) (sccm) (mm) Pre- 30 1700 24 50 200 10 27 ferred Low 25 1700 20 50 150 7 27 High 30 2000 27 100 300 12 47

[0073] TABLE 3 Process Operation Range of 2^(nd) Stage of Recipe (1) Press RF Power C₄F₈ CO Ar O₂ Gap (mT) (Watts) (sccm) (sccm) (sccm) (sccm) (mm) Pre- 60 1700 10 0 500 5 27 ferred Low 50 1700 10 0 450 5 27 High 60 2000 20 0 600 10 47

[0074] TABLE 4 Process Temperature Operation Range of Recipe (1) Top & Wall C-back E-back Temp Bottom Temp Side He side He (deg C.) (deg C.) (Torr) (Torr) Preferred 60 60 7 40 Low 50 50 5 30 High 70 80 10 50

Example 2

[0075] Highly selective SAC etching technique with the vertical island Contact etching at the same time

[0076] Etching Recipe (2):

[0077] Descum Etch:

[0078] 40 mT 1400W CF₄/Ar/O₂=80/160/20 sccm, 7 sec

[0079] ILD Etch-1:

[0080] 50 mT 1700W C₅F₈/CO/Ar/O₂=10/150/480/6 sccm, 60/60° C.,

[0081] Back He C/E=7/40T, 122 sec

[0082] I LD Etch-2:

[0083] 50 mT 1500W

[0084] C₅F₈/CO/Ar/O₂=6/00/500/6 sccm, 60/60° C.

[0085] Back He C/E=7/40T, 70 sec

[0086] Nitride Etch:

[0087] 50 mT 800W CHF₃/Ar/O₂=10/100/20 sccm, 60/60° C., Back He C/E=7/40T, 9 sec, Process Gap=37 mm

[0088] Etching Recipe (2) includes C₅F₈ chemistries, which is more selective to SiN than C₄F₈, due to the higher C/F atomic-ratio, and could generate more carbon rich polymerization. However etching recipe (2) described above achieved vertical contact profile all over the wafer with greater than 87° walls at the 0.27 μm hole size.

[0089] Conventional highly selective SAC etching with C₅F₈ chemistries give slightly tapered profiles with around 82-84° at the 0.27 μm hole size. So the contact resistance would be extremely improved in the present invention, giving much improved device function with the present invention approach described above.

[0090] In the SAC portion profile, the shortest distance with etching recipe (2) between the poly gate electrode corners ensured a margin approximately 2.0 times longer than that of conventional SAC etching recipes after the bottom nitride removal. Additionally, in this Example 2 recipe, the resulting nitride corner was greater than 620 Å all over the wafer.

[0091] Resulting from a study of the dissociation state of C₅F₈ based on enthalpies delta-H, it is already known that C₅F₈ is mainly dissociated into CF and CF₂ radicals and produces more carbon rich element in the plasma (3). Moreover it has been known widely that the fluorocarbon radicals react with CO to reduce fluorine from the bulk plasma (4).

[0092] The C₅F₈ chemistries described in etching recipe (2) gave optimized polymerization for the highly selective SAC etching and the reaction with CO in the bulk plasma gave more carbon rich radicals, such as CF and CF₂, and provided the highly selective SAC etching with the vertical island Contact etching at the same time.

[0093] The C₅F₈ chemistries described in etching recipe (2) result in a small slit between gate electrodes, having a minimum bottom dimension of 0.05 μm, without any etch stop due to the optimized polymerization and the effect of the reaction with CO. The process of the invention not only increased the process margins but also the process capability for future SAC schemes.

[0094] In addition, compared with conventional SAC etching, the present two stage etching approach with C₅F₈ chemistries described in etching recipe (2) would extend MTBC approximately twice and more.

Example 3

[0095] Highly selective and high etch rate SAC etching technique with the vertical island Contact etching at the same time

[0096] Etching Recipe (3):

[0097] Descum Etch:

[0098] 40 mT 1400W CF₄/Ar/O₂=80/160/20 sccm, 7 sec

[0099] ILD Etch-1:

[0100] 30 mT 1700W

[0101] C₄F₈/CO/Ar/O₂=25/50/250/10 sccm, 60/60° C.,

[0102] Back He C/E=7/30T, 45 sec

[0103] ILD Etch-2:

[0104] 50 mT 1500W C₅F₈/CO/Ar/O₂=10/00/500/10 sccm, 60/60° C.

[0105] Back He C/E=7/30T, 90 sec

[0106] Nitride Etch:

[0107] 50 mT 800W CHF₃/Ar/O₂=10/100/20 sccm,

[0108] Process Gap=37 mm,

[0109] Back He C/E=7/40T, 9 sec

[0110] This example combined the benefits of C₄F₈ chemistry in Example 1 with the benefits of C₅H₈ chemistry in Example 2 and gave highly selective and high etch rate SAC etching with the vertical island Contact etching at the same time.

[0111] So Etching recipe (3) would be one example of the ultimate SAC etching technique to have a total solution for current ULSI fabrication.

[0112] Further etching recipes are provided below. These recipes could maintain about 700 from the corner of the poly gate, which is approximately 2.0 times longer than conventional SAC processes.

[0113] Etching Recipe (4):

[0114] Descum Etch:

[0115] 40 mT 1400W CF₄/Ar/O₂=80/160/20 sccm, 7 sec

[0116] 1^(st) Stage:

[0117] 30 mT 1700W C₄F₈/CO/Ar/O₂=20/50/250/10 sccm

[0118] Back He C/E=10/40T, 45 sec

[0119] 2^(nd) Stage:

[0120] 45 mT 1800W C₅F₈/CO/Ar/O₂=10/00/500/10 sccm,

[0121] Back He C/E=10/40T, 85 sec

[0122] Nitride Etch:

[0123] 50 mT 800W CHF₃/Ar/O₂=10/100/20 sccm, Process Gap 37 mm,

[0124] Back He C/E=7/40T, 12 sec

[0125] Etching Recipe (5):

[0126] Descum Etch: 40 mT 1400W CF₄/Ar/O₂=80/160/20 sccm, 7 sec

[0127] 1^(st) Stage:

[0128] 30 mT 1700W C₄F₈/CO/Ar/O₂=20/50/250/10 sccm

[0129] Back He C/E=10/40T, 45 sec

[0130] 2^(nd) Stage:

[0131] 45 mT 1800W C₅F₈/CO/Ar/O₂/CF₄=15/00/500/15/10 sccm,

[0132] Back He C/E=10/40T, 75 sec

[0133] Nitride Etch:

[0134] 50 mT 800W CHF₃/Ar/O₂=10/100/20 sccm,

[0135] Process Gap=37 mm,

[0136] Back He C/E=7/40T, 12 sec TABLE 5 Process Operation Range of 2^(nd) Stage of Recipe (3), (4) and (5) Press. RF Power C₅F₈ CO Ar O₂ CF₄ Gap (mT) (Watts) (sccm) (sccm) (sccm) (sccm) (sccm) (mm) Preferred 45 1800 15 0 500 15 10 27 Low 40 1500 6 0 400 5 0 27 High 50 2000 20 0 600 20 10 47

[0137] TABLE 6 Process Temperature Operation Range of Recipe (3), (4) and (5) Top & Wall C-back E-back Temp Bottom Temp Side He side He (deg C.) (deg C.) (Torr) (Torr) Preferred 60 60 7 40 Low 50 50 5 30 High 70 80 10 50

[0138] Simply increased gas flow rate of C₅F₈ and O₂ while maintaining the same ratio as the 2^(nd) stage of Recipe (3) resulted in the etch stop phenomena beginning in a narrow slit, especially when the gas ratio of C₅F₈+O₂/Ar was bigger than 5%, regardless of the fact that the oxide etch rate and selectivity to nitride both increase. In order to eliminate the etch stop issue in higher gas flow ranges or higher gas ratios, it was sufficient to mix one more gas (at least) which could generate CF₃+ ion easily, such as CF₄, C₂F₆ and C₃F₈. Thus, SAC etching using a recipe such as Recipe (5) could be performed sucessfully without etch stop. The etching rate of the 2^(nd) stage of Recipe 5 was approximately 6000 Å/min on a TEOS wafer, which was approximately twice faster than that with a conventional SAC etching recipe.

[0139] Etching recipes using C₄F₆, which is a more carbon-rich chemistry compared to C₅F₈, are the same as above, with C₄F₆ substituted for C₅F₈.

[0140] Wafers were obtained having the following properties: (thickness is given in the unit of A (angstrom)) C₅F₈ process:

[0141] Wafer 11—45 mT/1800W/10 C₅F₈/500 Ar/10 O₂/60deg C. Btm/85 sec

[0142] Result: Center 780-860 (2sac), 730-840 (3sac) Edge 700-840 (2sac), 700-840 (3sac)

[0143] Wafer 5—45 mT/1800W/11 C₅F₈/500 Ar/9 O₂/60deg C. Btm/85 sec

[0144] Result: Center 810-930 (2sac), 760-930 (3sac) Edge 970-1190 (2sac), 910-1050 (3sac)

[0145] Wafer 6—45 mT/1800W/9 C₅F₈/500 Ar/11 O₂/60deg C. Btm/85 sec

[0146] Result: Center 650-690 (2sac), 690-740 (3sac) Edge 700-750 (2sac), 690-750 (3sac)

[0147] Wafer 9—45 mT/1800W/15 C₅F₈/500 Ar/15 O₂/10 CF₄/60deg C. Btm/75 sec

[0148] Result: Center 710-780 (2sac), 700-780 (3sac) Edge 900-1130 (2sac), 820-910 (3sac)

[0149] Wafer 8—45 mT/1800W/12 C₅F₈/500 Ar/8 O₂/60deg C. Btm/85 sec

[0150] Result: Etch Stop

[0151] C₄F₆ Process:

[0152] Wafer 12—45 mT/1800W/10 C₄F₆/500 Ar/10 O₂/60deg C. Btm/85 sec

[0153] Result: Center 740-780 (2sac), 720-820 (3sac) Edge 760-920 (2sac), 730-910 (3sac)

[0154] Wafer 1—45 mT/1800W/11 C₄F₆/500 Ar/9 O₂/60deg C. Btm/85 sec

[0155] Result: Center 740-850 (2sac), 730-900 (3sac) Edge 820-950 (2sac), 720-1080 (3sac)

[0156] Wafer 2—45 mT/1800W/9 C₄F₆/500 Ar/11 O₂/60deg C. Btm/85 sec

[0157] Result: Center 700-800 (2sac), 700-850 (3sac) Edge 700-770 (2sac), 700-780 (3sac)

[0158] Wafer 3—45 mT/1800W/11 C₄F₆/500 Ar/11 O₂/60deg C. Btm/85 sec

[0159] Result: Center 890-900 (2sac), 760-860 (3sac) Edge 970-1000 (2sac), 740-1010 (3sac)

[0160] Wafer 4—45 mT/1800W/15 C₄F₆/500 Ar/15 O₂/10 CF₄/60deg C. Btm/75 sec

[0161] Result: Center 740-860 (2sac), 770-840 (3sac) Edge 910-1020 (2sac), 740-1010 (3sac)

[0162] Wafer 7—45 mT/1800W/12 C₄F₆/500 Ar/8 O₂/60deg C. Btm/85 sec

[0163] Result: Etch Stop

[0164] The data obtained according to the present invention provide the following conclusions:

[0165] For C₅F₈ Chemistries:

[0166] 1. The gas ratio of CsF₈/O₂ is most preferably between 0.818 and 1.222.

[0167] 2. The gas ratio of C₅F₈+O₂/Ar is preferably between 0.02 and 0.05, more preferably between 0.03 and 0.04.

[0168] For C₄F₆ Chemistries:

[0169] 1. The gas ratio of C₄F₆/O₂ is most preferably between 0.818 and 1.222.

[0170] 2. The gas ratio of C₄F₆+O₂/Ar is preferably between 0.02 and 0.05, more preferably between 0.03 and 0.04.

[0171] 3. As noted above for the case of C₅F₈ chemistries, when the gas ratio of C₄F₆+O₂/Ar is greater than 0.05, additional gas is required such as CF₄, C₂F₆, C₃F₈ or C₄F₁₀ (CnF_(2n)+2).

[0172] Since there is not a big difference seen between recipes using C₄F₆ and those using C₅F₈, either recipe would be an example of a SAC etching technique to have a total solution for current ULSI fabrication. These etching recipes could also be applied to other processes such as Via contact process or Dual Damascene process.

[0173] As device integration increases and device feature size is reduced, it gets more difficult to fill insulating material in the small slit between gate electrodes for SAC scheme. Also it is known that interconnect delay caused by wiring capacitance increases drastically and degrades circuit performance of LSIs.

[0174] In order to address these issues for the next generation SAC scheme, it is expected to apply SOG films having as the main ingredients, SiOH or SiOF.

[0175] For a new SAC scheme, a PFC and CO combination plasma described in ILD-1 step of the above etching recipes or no CO combination plasma described in ILD-2 step of the above etching recipes can etch SOG films same as the conventional oxides.

[0176] Additionally, by replacing the O₂ with N₂, these two step etching approaches can realize the same timing etching technique of SAC and Contact etching for the conventional oxide scheme and new materials as the main ingredients of SiOH or SiOF.

[0177] Therefore, the method of the present invention is useful and advances SAC etching technology in ULSI fabrication since the etching rate of SOG film is almost the same as that of conventional oxide films such as PSG, NSG, TEOS and Thermally-grown-SiO₂.

[0178] And there sometimes happens process issues on CMP process step. Therefore the film stack of a wafer (50) is not always exactly same. In case of FIG. 2., TEOS (52) underneath of Photoresist may have some film variation on wafer-to-wafer. And then if a film variation on wafer-to-wafer exists much on incoming material, SAC etching could be controlled by End Point Detection System to eliminate any mistakes on etch process.

[0179] For the 1st stage etching, C—F₂ radical (260 nm) and C—N radical (387 nm) spectra are very useful to detect 1st endpoint for Nitride liner (57) on Nitride cap (55) in case of CO contained plasma. And for the 2nd stage etching, C—F₂ radical (260 nm) and C—O radical (219 nm) are very useful to detect 2nd endpoint for the Bottom Nitride liner (57). Moreover while etching oxide films, C—O is produced as by-product, so no-CO plasma as in 2^(nd) stage etching recipe in this present invention, would have another advantage to detect end point much easier.

[0180] Alternative optical emission spectra are described in the followings; CF 240 nm, 256 nm, CF₂ 252 nm, 255 nm, 263 nm, 27 nm, 275 nm CO 239 nm, 249 nm, 283 nm, 313 nm, 33 nm, 349 nm, 370 nm, 45 nm, 484 nm, 520 nm, 561 nm CN 359 nm, 418 nm, 422 nm, 647 nm, 693 nm, 709 nm, 785 nm 

1. A method for SAC etching comprising: a) etching a wafer having a silicon oxide layer above a silicon nitride layer present thereon with a first etching gas comprising a first perfluorocarbon and carbon monoxide and, b) etching the resultant wafer having an initially etched silicon nitride thereon with a second etching gas comprising a second perfluorocarbon in the absence of carbon monoxide.
 2. The method of claim 1, wherein said step a) and step b) are each performed at a plasma producing RF power of greater than 1500W and at a pressure of 50 mTorr or less.
 3. The method of claim 1, wherein said step a) is performed at a plasma producing RF power of at least 1700W and at a pressure of 30 mTorr or less.
 4. The method of claim 1, wherein said step b) is performed at a plasma producing RF power of at least 1700W and at a pressure of 30 mTorr or less.
 5. The method of claim 3, wherein said step b) is performed at a plasma producing RF power of at least 1500W and at a pressure of 50 mTorr or less.
 6. The method of claim 1, wherein said step a) is performed at a plasma producing RF power and pressure sufficient to generate an etching rate of at least about 6000 Å/min.
 7. The method of claim 1, wherein said first perfluorocarbon and said second perfluorocarbon are the same.
 8. The method of claim 1, wherein said first perfluorocarbon and said second perfluorocarbon are different from one another.
 9. The method of claim 1, wherein said first perfluorocarbon is C₃F₆, C₄F₆, C₄F₈ or C₅F₈.
 10. The method of claim 1, wherein said second perfluorocarbon is C₃F₆, C₄F₆, C₄F₈ or C₅F₈.
 11. The method of claim 9, wherein said first perfluorocarbon is C₄F₈ or C₅F₈.
 12. The method of claim 10, wherein said second perfluorocarbon is C₄F₈ or C₅F₈.
 13. The method of claim 1, wherein said method further comprises: descumming prior to said step a), wherein said descumming is performed with an etch gas of a third perfluorocarbon and either of O₂ or N₂ for a period of 10 seconds or less, wherein said third perfluorocarbon can be the same or different from either of said first or second perfluorocarbons.
 14. The method of claim 1, wherein said method further comprises: removing nitride in a final nitride etch, wherein said final nitride etch is performed after said step b) for a time period sufficient to remove excess nitride and etch into the Si wafer to a level of up to about 200 Å.
 15. The method of claim 1, wherein said first etching gas comprises said first perfluorocarbon and carbon monoxide and further comprises an inert gas and a gas selected from the group consisting of O₂ and N₂.
 16. The method of claim 15, wherein said first etching gas is a mixture of 20-27 sccm of first perfluorocarbon, 50-100 sccm of CO, 150-300 sccm of inert gas and 7-12 sccm of O₂.
 17. The method of claim 15, wherein said first etching gas is a mixture of 20-27 sccm of first perfluorocarbon, 50-100 sccm of CO, 150-300 sccm of inert gas and 70-120 sccm of N₂.
 18. The method of claim 1, wherein said second etching gas comprises said second perfluorocarbon, and further comprises an inert gas and a gas selected from the group consisting Of O₂ and N₂, in the substantial absence of carbon monoxide.
 19. The method of claim 18, wherein said second etching gas comprises a mixture of 10-20 sccm of second perfluorocarbon, 450-550 sccm of inert gas and 5-10 sccm of O₂.
 20. The method of claim 18, wherein said second etching gas comprises a mixture of 10-20 sccm of second perfluorocarbon, 450-550 sccm of inert gas and 50-100 sccm of N₂.
 21. The method of claim 15, wherein said first etching gas comprises said first perfluorocarbon and O₂ in a flow ratio of from 2:1 to 3:1.
 22. The method of claim 18, wherein said second etching gas comprises said second perfluorocarbon and O₂ in a flow ratio of from 2:1 to 3:1.
 23. The method of claim 1, wherein said wafer is maintained at a bottom temperature of from 50-60° C. throughout step a), step b) or both. 